Variation-Aware Advanced CMOS Devices and SRAM
Changhwan Shin
Jun 2016 · Springer Series in Advanced Microelectronics Book 56 · Springer
Ebook
140
Pages
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About this ebook
This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM.
The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reader with a deep understanding of the major random variation sources, and the characterization of each random variation source. Furthermore, the book presents various CMOS device designs to surmount the random variation in future CMOS technology, emphasizing the applications to SRAM.
About the author
Prof. Changhwan Shin is an Assistant Professor in School of Electrical and Computer Engineering in University of Seoul. Prof. Shin is a graduate of Korea University (BE) and University of California Berkeley (Ph.D). Also, he is Technical Committee Members for IEEE SOI Conference and European Solid-State Device Research Conference (ESSDERC). His research activities cover Electronic Devices and Integrated Circuits; Advanced electronic device architecture for various types of System-on-Chip(SoC) memory and logic devices/ All-in-one Variability Analysis for Nanometer-scale Electronic Devices/ Post-Silicon Technology (CNT, Graphene) & Bio-applications/ Device-and-Circuit Co-optimization: "Low-Level" Digital/Analog Circuit Design Methodology Development/ Programmable Chip Development using Advanced Electronic Devices.
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